Standard cell libraries are commonly employed for integrated circuit design. In this design approach, circuit functions (such functions include logic gates such as AND and OR gates, as well as sequential logic elements such as flip flops) each have a corresponding library cell type. Each cell type corresponds to one or more library cells. Library cells include a detailed device-level layout for providing the corresponding circuit function. For example, a cell type can be AND2 (a 2 input AND gate). Several different AND2 cells can be included in a typical cell library (e.g., having different drive strengths and/or different threshold voltages). Circuit design with a cell library typically relies on automated selection of cells from the library to perform the required circuit functions. In this manner, a detailed layout design is automatically obtained from a functional circuit design.
The design of cell libraries tends to be driven by minimization of cell physical area subject to other design constraints (e.g., on drive strength and/or threshold voltage) and subject to a minimum feature size constraint. The minimum feature size constraint (also known as the design rule distance) is a key consideration in integrated circuit design. In the context of commercial integrated circuit fabrication, the minimum feature size L is usually defined operationally. More specifically, a fabrication vendor will usually agree to meet performance specifications only if the minimum feature size in the circuit layout provided to the vendor is greater than or equal to L. Thus L can vary from vendor to vendor at a given time, and generally tends to decrease over time as fabrication technology advances. For state of the art fabrication facilities, L is presently well under 0.25 μm, and is expected to significantly decrease in the future.
Cell libraries can also be classified in terms of a minimum distance. Thus a 0.25 μm cell library is a cell library in which all cells have a minimum feature size no less than 0.25 μm. Such a cell library can be used to provide layout designs for any fabrication facility providing an L of 0.25 μm or less. Typically, all cells in a library are designed according to the same design rules (e.g., 0.25 μm design rules). Typically, L as provided by fabrication vendors decreases in a stepwise manner, and each L in the sequence is often referred to as a generation. For example, in Silicon the fabrication generations are 0.25 μm, 0.18 μm, 0.13 μm, 90 nm, and 65 nm. Future decreases in L are also expected to follow this generational pattern. Conventional cell libraries follow the same generational pattern.
However, in practice fabrication capability improves continuously. A significant effect of this continuous improvement is a generally decreasing process variability over time within a generation. When a new generation is first introduced, the process variability is largest, and then decreases over time. This behavior poses a difficult problem to the circuit designer, since the transition to a new generation tends to be accompanied by an increase in process variability. This increase in process variability tends to decrease yield (e.g., by increasing leakage). In some cases, this decrease in yield is significant enough to complicate the decision of when to change generations.
One possible solution to this problem would be to design an intermediate library (e.g., a 0.14 μm library) to ease the generational transition (e.g., from 0.15 μm to 0.13 μm). A 0.13 μm fabrication facility should provide high yields at 0.14 μm, even when the 0.13 μm capability is first introduced. However, this approach is unattractive, since any designs made with such a 0.14 μm library would have to be completely redone once the fabrication technology improves to the point where 0.13 μm designs have sufficient yield. Such intra-generational redesign is highly undesirable, since it adds cost and complexity to the design process.
The requirement for expensive intra-generational redesign follows from the usual assumptions of cell library design, especially the assumption of minimal cell area subject to other constraints. Thus alternative approaches to cell library design (i.e., some kind of scalable library) can be considered to help alleviate this problem. Scalable library approaches considered in the art do not provide a sufficient solution to the intra-generational redesign problem identified above. Many known scalable libraries (e.g., as considered in U.S. Pat. No. 5,598,347, U.S. Pat. No. 5,619,420, U.S. Pat. No. 5,663,662, U.S. Pat. No. 6,336,207, and U.S. Pat. No. 6,467,068) are concerned with providing cells having a scalable drive strength (typically by scaling transistor width). Since drive strength has no relation to the design rule distance, such scaling has no bearing on intra-generational redesign.
Another known cell library design approach that makes use of scalable cells is based on first obtaining a circuit layout using automatic design with standard cells, then automatically optimizing the layout by modifying cells. Typically only the critical paths in the layout are thus optimized, and modifying the standard cells can include scaling them. Such approaches are considered in U.S. Pat. No. 5,872,717 and U.S. Pat. No. 5,880,967. Such approaches are generally contemplated in relation to fixed design rules, especially since it would make little sense to have different design rules for the standard cells and for the modified standard cells. Thus this kind of library scaling also does not address the intra-generational redesign problem.
Known cell libraries also include cell libraries having two (or more) cells corresponding to the same circuit function (or cell type as indicated above), where the cells have different transistor channel lengths (or gate lengths). Transistors with shorter channels tend to have increased speed, but also have increased leakage current. Transistors with longer channels tend to have reduced speed and reduced leakage current. Threshold voltage also tends to decrease with channel length. Provision of cells having varying channel length in the same library allows automatic standard cell library design tools to effectively include such tradeoffs between speed, leakage and threshold voltage in design. Examples of such approaches include U.S. Pat. No. 6,427,226 and U.S. Pat. No. 6,769,110. However, these approaches also do not address the problem of intra-generational redesign.
Accordingly, it is an object of the invention to provide a scalable standard cell library to reduce intra-generational redesign.